35 search results - page 2 / 7 » Characterizing the branch misprediction penalty |
PLDI
2005
ACM
13 years 10 months ago
2005
ACM
Code placement techniques have traditionally improved instruction fetch bandwidth by increasing instruction locality and decreasing the number of taken branches. However, traditio...
MICRO
1999
IEEE
13 years 9 months ago
1999
IEEE
Branch mispredictions are a major obstacle to exploiting instruction-level parallelism, at least in part because all instructions after a mispredicted branch are squashed. However...
IPPS
2005
IEEE
13 years 10 months ago
2005
IEEE
Current processors exploit out-of-order execution and branch prediction to improve instruction level parallelism. When a branch prediction is wrong, processors flush the pipeline ...
MICRO
2005
IEEE
13 years 10 months ago
2005
IEEE
Predicated execution has been used to reduce the number of branch mispredictions by eliminating hard-to-predict branches. However, the additional instruction overhead and addition...
APCSAC
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper describes a new on-demand wakeup prediction policy for instruction cache leakage control that achieves better leakage savings than prior policies, and avoids the perform...