7 search results - page 2 / 2 » Checking equivalence of quantum circuits and states |
GLVLSI
2007
IEEE
13 years 9 months ago
2007
IEEE
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...
ICCAD
1999
IEEE
13 years 9 months ago
1999
IEEE
In this paper we present new methods for fast justification and propagation in the implication graph (IG) which is the core data structure of our SAT based implication engine. As ...