GLVLSI 2007 - PDF Preprint Papers

GLVLSI 2007 Great Lakes Symposium on VLSI

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GLVLSI
2007
IEEE

328views VLSI» more GLVLSI 2007»

New timing and routability driven placement algorithms for FPGA synthesis

13 years 11 months ago

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We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accura...

Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong H...

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Id	Views	Title	Status

1	328	New timing and routability driven placement algorithms for FPGA synthesis	claim
2	258	I-cache multi-banking and vertical interleaving	claim
3	211	Multi-processor operating system emulation framework with thermal feedback for systems-on-chip	claim
4	194	Probabilistic maximum error modeling for unreliable logic circuits	claim
5	192	Area efficient loop filter design for charge pump phase locked loop	claim
6	189	Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems	claim
7	187	DAG based library-free technology mapping	claim
8	186	Block placement to ensure channel routability	claim
9	181	A 5 GHz wide band input and output matched low noise amplifier	claim
10	177	Improvements for constraint solving in the systemc verification library	claim
11	173	Modeling and estimating leakage current in series-parallel CMOS networks	claim
12	172	The effect of temperature on cache size tuning for low energy embedded systems	claim
13	171	Combinational equivalence checking for threshold logic circuits	claim
14	167	A new approach to logic synthesis of multi-output boolean functions on pal-based CPLDS	claim
15	166	Efficient pipelining for modular multiplication architectures in prime fields	claim
16	164	Active bank switching for temperature control of the register file in a microprocessor	claim
17	162	Design of an UHF RFID transponder for secure authentication	claim
18	162	Utilizing custom registers in application-specific instruction set processors for register spills elimination	claim
19	158	Design of a versatile and cost-effective hybrid floating-point/LNS arithmetic processor	claim
20	158	RT-level vector selection for realistic peak power simulation	claim
21	154	A design kit for a fully working shared memory multiprocessor on FPGA	claim
22	154	Analyzing and modeling process balance for sub-threshold circuit design	claim
23	153	Address generation for nanowire decoders	claim
24	152	Optimization techniques for BDD-based bisimulation computation	claim
25	151	Hand-in-hand verification of high-level synthesis	claim
26	142	Three-valued automated reasoning on analog properties	claim
27	141	Transition-activity aware design of reduction-stages for parallel multipliers	claim
28	141	A synchronization algorithm for local temporal refinements in perfectly synchronous models with nested feedback loops	claim
29	140	Structured and tuned array generation (STAG) for high-performance random logic	claim
30	139	Synthesis of irregular combinational functions with large don't care sets	claim
31	135	Exact sat-based toffoli network synthesis	claim
32	134	Sleep transistor distribution in row-based MTCMOS designs	claim
33	126	An asynchronous fpga logic cell implementation	claim
34	115	Novel architectures for efficient (m, n) parallel counters	claim
35	114	Design of mixed gates for leakage reduction	claim
36	111	Probabilistic gate-level power estimation using a novel waveform set method	claim
37	107	Side-channel resistant system-level design flow for public-key cryptography	claim
38	106	Floorplan repair using dynamic whitespace management	claim

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