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CODES
2010
IEEE
13 years 4 months ago
Automatic parallelization of embedded software using hierarchical task graphs and integer linear programming
The last years have shown that there is no way to disregard the advantages provided by multiprocessor System-on-Chip (MPSoC) architectures in the embedded systems domain. Using mu...
Daniel Cordes, Peter Marwedel, Arindam Mallik
FPL
2010
Springer
124views Hardware» more  FPL 2010»
13 years 4 months ago
Finding System-Level Information and Analyzing Its Correlation to FPGA Placement
One of the more popular placement algorithms for Field Programmable Gate Arrays (FPGAs) is called Simulated Annealing (SA). This algorithm tries to create a good quality placement ...
Farnaz Gharibian, Lesley Shannon, Peter Jamieson
GLOBECOM
2010
IEEE
13 years 4 months ago
Passively Controllable Smart Antennas
Abstract-- This work deals with devising a secure, powerefficient, beam-steerable and on-chip transmission system for wireless sensor networks. A passively controllable smart (PCS)...
Javad Lavaei, Aydin Babakhani, Ali Hajimiri, John ...
IPPS
2010
IEEE
13 years 4 months ago
Structuring the execution of OpenMP applications for multicore architectures
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...
François Broquedis, Olivier Aumage, Brice G...
ICCAD
2009
IEEE
117views Hardware» more  ICCAD 2009»
13 years 3 months ago
Binning optimization based on SSTA for transparently-latched circuits
With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transpa...
Min Gong, Hai Zhou, Jun Tao, Xuan Zeng