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TVLSI
2008
85views more  TVLSI 2008»
13 years 5 months ago
Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors
Chip-Multi-Processors (CMP) utilize multiple energy-efficient Processing Elements (PEs) to deliver high performance while maintaining an efficient ratio of performance to energy-c...
A. Elyada, Ran Ginosar, Uri Weiser
HPCA
2005
IEEE
14 years 5 months ago
Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture
This paper studies the impact of L2 cache sharing on threads that simultaneously share the cache, on a Chip Multi-Processor (CMP) architecture. Cache sharing impacts threads non-u...
Dhruba Chandra, Fei Guo, Seongbeom Kim, Yan Solihi...
ICCD
2002
IEEE
135views Hardware» more  ICCD 2002»
14 years 2 months ago
Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip
We present a co-simulation environment for multiprocessor architectures, that is based on SystemC and allows a transparent integration of instruction set simulators (ISSs) within ...
Luca Benini, Davide Bertozzi, Davide Bruni, Nicola...
MICRO
2007
IEEE
128views Hardware» more  MICRO 2007»
13 years 11 months ago
A Framework for Providing Quality of Service in Chip Multi-Processors
The trends in enterprise IT toward service-oriented computing, server consolidation, and virtual computing point to a future in which workloads are becoming increasingly diverse i...
Fei Guo, Yan Solihin, Li Zhao, Ravishankar Iyer
DATE
2008
IEEE
113views Hardware» more  DATE 2008»
13 years 7 months ago
Run-time Spatial Mapping of Streaming Applications to a Heterogeneous Multi-Processor System-on-Chip (MPSOC)
In this paper, the problem of spatial mapping is defined. Reasons are presented to show why performing spatial mappings at run-time is both necessary and desirable and criteria fo...
Philip K. F. Hölzenspies, Johann Hurink, Jan ...