2 search results - page 1 / 1 » Choosing an Error Protection Scheme for a Microprocessor's L... |
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract-- We deconstruct and compare the two dominant existing approaches for L1 data cache (L1D) error protection, with respect to performance, L2 cache bandwidth, power, and are...
TCAD
2008
13 years 4 months ago
2008
Soft-error induced reliability problems have become a major challenge in designing new generation microprocessors. Due to the on-chip caches' dominant share in die area and tr...