53 search results - page 1 / 11 » Circuit Synthesis of Clock Distribution Networks Based on No... |
ISCAS
1994
IEEE
13 years 9 months ago
1994
IEEE
ISCAS
1995
IEEE
13 years 9 months ago
1995
IEEE
DAC
2008
ACM
14 years 6 months ago
2008
ACM
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR g...
DAC
2009
ACM
13 years 10 months ago
2009
ACM
We present an unconventional clock distribution that emphasizes flexibility and layout independence. It suits a variety of applications, clock domain shapes and sizes using a modu...
GLVLSI
2010
IEEE
13 years 10 months ago
2010
IEEE
Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as ...