24 search results - page 1 / 5 » Circuit techniques for low-power CMOS GSI |
PATMOS
2004
Springer
13 years 10 months ago
2004
Springer
A full-adder implemented by combining branch-based logic and pass-gate logic is presented in this contribution. A comparison between this proposed full-adder (named BBL PT) and its...
ISLPED
1996
ACM
13 years 8 months ago
1996
ACM
ISLPED
1998
ACM
13 years 8 months ago
1998
ACM
IWSOC
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper explores the design and optimization of Quasi-Floating Gate MOS techniques to lowvoltage/low-power digital circuitry. The simulated power consumption of standard CMOS g...
DAC
1999
ACM
13 years 9 months ago
1999
ACM
Dual threshold technique has been proposed to reduce leakage power in low voltage and low power circuits by applying a high threshold voltage to some transistors in non-critical p...