64 search results - page 2 / 13 » Classifying load and store instructions for memory renaming |
ISCA
1998
IEEE
13 years 9 months ago
1998
IEEE
For maximum performance, an out-of-order processor must issue load instructions as early as possible, while avoiding memory-order violations with prior store instructions that wri...
IEEEPACT
2002
IEEE
13 years 9 months ago
2002
IEEE
Many modern embedded processors (esp. DSPs) support partitioned memory banks (also called X-Y memory or dual bank memory) along with parallel load/store instructions to achieve co...
MICRO
1998
IEEE
13 years 9 months ago
1998
IEEE
Load latency remains a significant bottleneck in dynamically scheduled pipelined processors. Load speculation techniques have been proposed to reduce this latency. Dependence Pred...
ISCA
2005
IEEE
13 years 10 months ago
2005
IEEE
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
ISCA
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper presents a hardware-based dynamic optimizer that continuously optimizes an application’s instruction stream. In continuous optimization, dataflow optimizations are p...