64 search results - page 4 / 13 » Classifying load and store instructions for memory renaming |
IEEEPACT
2002
IEEE
13 years 10 months ago
2002
IEEE
Memory dependence prediction allows out-of-order issue processors to achieve high degrees of instruction level parallelism by issuing load instructions at the earliest time withou...
CASES
2003
ACM
13 years 11 months ago
2003
ACM
In an embedded system, the cost of storing a program onchip can be as high as the cost of a microprocessor. Compressing an application’s code to reduce the amount of memory requ...
HPCA
2006
IEEE
14 years 6 months ago
2006
IEEE
Allowing loads to issue out-of-order with respect to earlier unresolved store addresses is very important for extracting parallelism in large-window superscalar processors. Blindl...
HPCA
2002
IEEE
13 years 10 months ago
2002
IEEE
As the frequency gap between main memory and modern microprocessor grows, the implementation and efficiency of on-chip caches become more important. The growing latency to memory ...
SEUS
2009
IEEE
14 years 15 days ago
2009
IEEE
Abstract. In this paper we explore the combination of a time-predictable chipmultiprocessor system with the single-path programming paradigm. Time-sliced arbitration of the main me...