2 search results - page 1 / 1 » Clock buffer polarity assignment for power noise reduction |
ICCAD
2006
IEEE
13 years 10 months ago
2006
IEEE
Abstract—Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polariti...
ICCD
2004
IEEE
14 years 1 months ago
2004
IEEE
We present a method for incorporating crosstalk reduction criteria into global routing under an innovative power supply architecture, while considering the constraints imposed by ...