205 search results - page 41 / 41 » Clock gating architectures for FPGA power reduction |
DAC
2006
ACM
14 years 6 months ago
2006
ACM
With ever-increasing power density and cooling costs in modern high-performance systems, dynamic thermal management (DTM) has emerged as an effective technique for guaranteeing th...
DAC
2005
ACM
14 years 6 months ago
2005
ACM
ASIC provides more than an order of magnitude advantage in terms of density, speed, and power requirement per gate. However, economic (cost of masks) and technological (deep micro...
TC
2008
13 years 5 months ago
2008
Cryptanalysis of ciphers usually involves massive computations. The security parameters of cryptographic algorithms are commonly chosen so that attacks are infeasible with availabl...
HPCA
2006
IEEE
14 years 5 months ago
2006
IEEE
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
DAC
2006
ACM
14 years 6 months ago
2006
ACM
Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several othe...