12 search results - page 2 / 3 » Clock network minimization methodology based on incremental ... |
ISLPED
2010
ACM
13 years 4 months ago
2010
ACM
Structured ASICs provide an exciting middle ground between FPGA and ASIC design methodologies. Compared to ASIC, structured ASIC based designs require lower non recurring engineer...
DAC
2008
ACM
14 years 5 months ago
2008
ACM
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR g...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
Novel methodology and algorithms to seamlessly integrate logic synthesis and physical placement through a transformational approach are presented. Contrary to most placement algor...
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
— A methodology based on supply voltage optimization for lowering the power consumption and temperature fluctuations induced skew of clock distribution networks is proposed in th...
VLSID
2007
IEEE
14 years 5 months ago
2007
IEEE
Crosstalk noise in the clock network of digital circuits is often detected late in the design cycle, sometimes as late as after first silicon. It is therefore necessary to fix cros...