96 search results - page 1 / 20 » Clock-Aware Placement for FPGAs |
FPL
2007
Springer
13 years 11 months ago
2007
Springer
The programmable clock networks in FPGAs have a significant impact on overall power, area, and delay. Not only does the clock network itself dissipate a significant amount of powe...
IFIP
1999
Springer
13 years 9 months ago
1999
Springer
In this paper we describe Frontier, an FPGA placement system that uses design macro-blocks in conjuction with a series of placement algorithms to achieve highly-routable and high-...
EH
2004
IEEE
13 years 8 months ago
2004
IEEE
Field programmable gate arrays (FPGAs) are becoming increasingly important implementation platforms for digital circuits. One of the necessary requirements to effectively utilize ...
ICCTA
2007
IEEE
13 years 8 months ago
2007
IEEE
In this paper, we propose a placement method for islandstyle FPGAs, based on fast yet very good initial placement followed by refinement using ultra-low temperature Simulated Anne...
FPGA
2000
ACM
13 years 8 months ago
2000
ACM
In this paper we introduce a new Simulated Annealingbased timing-driven placement algorithm for FPGAs. This paper has three main contributions. First, our algorithm employs a nove...