3 search results - page 1 / 1 » Cluster-based Simulated Annealing for Mapping Cores onto 2D ... |
DDECS
2008
IEEE
13 years 11 months ago
2008
IEEE
Abstract—In Network-on-Chip (NoC) application design, coreto-node mapping is an important but intractable optimization problem. In the paper, we use simulated annealing to tackle...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
We address the design of complex monolithic systems, where processing cores generate and consume a varying and large amount of data, thus bringing the communication links to the e...
ISVLSI
2002
IEEE
13 years 9 months ago
2002
IEEE
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...