Sciweavers

10 search results - page 1 / 2
» Code Compression and Decompression for Instruction Cell Base...
Sort
View
IPPS
2007
IEEE
13 years 11 months ago
Code Compression and Decompression for Instruction Cell Based Reconfigurable Systems
Code compression has been applied to embedded systems to minimize the silicon area utilized for program memories, and lower the power consumption. More recently, it has become a n...
Nazish Aslam, Mark Milward, Ioannis Nousias, Tughr...
FCCM
2007
IEEE
154views VLSI» more  FCCM 2007»
13 years 11 months ago
Code Compressor and Decompressor for Ultra Large Instruction Width Coarse-Grain Reconfigurable Systems
This paper presents a code compression and on-thefly decompression scheme suitable for coarse-grain reconfigurable technologies. A novel unit-grouping dictionary based compression...
Nazish Aslam, Mark Milward, Ioannis Nousias, Tughr...
ISSS
1999
IEEE
131views Hardware» more  ISSS 1999»
13 years 8 months ago
Compressed Code Execution on DSP Architectures
Decreasing the program size has become an important goal in the design of embedded systems target to mass production. This problem has led to a number of efforts aimed at designin...
Paulo Centoducatte, Ricardo Pannain, Guido Araujo
DATE
2006
IEEE
120views Hardware» more  DATE 2006»
13 years 10 months ago
System-level scheduling on instruction cell based reconfigurable systems
This paper presents a new operation chaining reconfigurable scheduling algorithm (CRS) based on list scheduling that maximizes instruction level parallelism available in distribut...
Ying Yi, Ioannis Nousias, Mark Milward, Sami Khawa...
TVLSI
2002
98views more  TVLSI 2002»
13 years 4 months ago
Minimizing memory access energy in embedded systems by selective instruction compression
We propose a technique for reducing the energy spent in the memory-processor interface of an embedded system during the execution of firmware code. The method is based on the idea ...
Luca Benini, Alberto Macii, Enrico Macii, Massimo ...