Code Compression and Decompression for Instruction Cell Based Reconfigurable Systems

Code compression has been applied to embedded systems to minimize the silicon area utilized for program memories, and lower the power consumption. More recently, it has become a necessity for multiple-issue architectures, such as VLIW and TTA, to permit a viable realization of these designs. In this paper, a code compression and decompression scheme suitable for newly emerging reconfigurable technologies is presented, which pose further challenges by having an order of magnitude higher memory requirement due to much wider instruction words than typical VLIW/TTA architectures. Two dictionary-based lossless compression schemes are implemented and compared for an example reconfigurable system. This paper looks at several conflicting design parameters, such as the compression ratio, silicon area and speed. Test programs for a 2D DCT, minimum error, wimax and H.264 have been evaluated with compression ratios in the range of 41% to 62% recorded with the best scheme.

• Type: Conference
• Year: 2007
• Where: IPPS
• Authors: Nazish Aslam, Mark Milward, Ioannis Nousias, Tughrul Arslan, Ahmet T. Erdogan
• Keywords: Code Compression, Compression Ratios, Distributed And Parallel Computing, IPPS 2007, Silicon Area