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» Collaborative Routing Architecture for FPGA
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FPGA
2005
ACM
90views FPGA» more  FPGA 2005»
13 years 10 months ago
Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits
Abstract—As the logic capacity of field-programmable gate arrays (FPGAs) increases, they are increasingly being used to implement large arithmetic-intensive applications, which ...
Andy Gean Ye, Jonathan Rose
FPGA
1998
ACM
180views FPGA» more  FPGA 1998»
13 years 9 months ago
A Novel Predictable Segmented FPGA Routing Architecture
Emil S. Ochotta, Patrick J. Crotty, Charles R. Eri...
FPGA
2008
ACM
155views FPGA» more  FPGA 2008»
13 years 6 months ago
A novel FPGA logic block for improved arithmetic performance
To improve FPGA performance for arithmetic circuits, this paper proposes a new architecture for FPGA logic cells that includes a 6:2 compressor. The new cell features additional f...
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
FPGA
2008
ACM
168views FPGA» more  FPGA 2008»
13 years 5 months ago
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs
The Field Programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an ...
Alessandro Cevrero, Panagiotis Athanasopoulos, Had...
FPGA
1999
ACM
142views FPGA» more  FPGA 1999»
13 years 9 months ago
Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems
Multi-FPGA systems are used as custom computing machines to solve compute intensive problems and also in the verification and prototyping of large circuits. In this paper, we addr...
Abdel Ejnioui, N. Ranganathan