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ICCD
2004
IEEE
112views Hardware» more  ICCD 2004»
14 years 1 months ago
Combined Channel Segmentation and Buffer Insertion for Routability and Performance Improvement of Field
In this paper, we propose a combined channel segmentation and buffer insertion approach, which minimizes the number of buffers inserted while satisfying the delay constraints for ...
Hu Huang, Joseph B. Bernstein, Martin Peckerar, Ji...
GLVLSI
2009
IEEE
155views VLSI» more  GLVLSI 2009»
13 years 11 months ago
Buffer design and optimization for lut-based structured ASIC design styles
The interconnection delay of pre-fabricated design style dominates circuit delay due to the heavily downstream capacitance. Buffer insertion is a widely used technique to split o...
Po-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, Yi-Yu Liu