Sciweavers

46 search results - page 1 / 10
» Combining Formal Refinement and Model Checking for Real-Time...
Sort
View
ENTCS
2006
142views more  ENTCS 2006»
13 years 4 months ago
Predicate Diagrams for the Verification of Real-Time Systems
We propose a format of predicate diagrams for the verification of real-time systems. We consider systems that are defined as extended timed graphs, a format that combines timed au...
Eun-Young Kang, Stephan Merz
CAV
2003
Springer
140views Hardware» more  CAV 2003»
13 years 8 months ago
Rabbit: A Tool for BDD-Based Verification of Real-Time Systems
Thispapergivesashort overviewofa model checking tool forreal-time systems. The modeling language are timed automata extended with concepts for modular modeling. The tool provides r...
Dirk Beyer, Claus Lewerentz, Andreas Noack
VLSID
2003
IEEE
180views VLSI» more  VLSID 2003»
14 years 5 months ago
Automating Formal Modular Verification of Asynchronous Real-Time Embedded Systems
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
Pao-Ann Hsiung, Shu-Yu Cheng
DATE
2004
IEEE
147views Hardware» more  DATE 2004»
13 years 8 months ago
Formal Refinement and Model Checking of an Echo Cancellation Unit
This article presents an approach, which combines theorem proving-based refinement with model checking for state based real-time systems. Our verification flow starts from UML sta...
Alexander Krupp, Wolfgang Müller 0003, Ian Ol...