362 search results - page 1 / 73 » Communication Mechanisms for Parallel DSP Systems on a Chip |
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
We consider the implication of deep sub-micron VLSI technology on the design of communication frameworks for parallel DSP systems-on-chip. We assert that distributed data transfer...
IEEEPACT
2000
IEEE
13 years 9 months ago
2000
IEEE
As on-chip integration matures, single-chip system designers must not only be concerned with component-level issues such as performance and power, but also with onchip system-leve...
NOCS
2007
IEEE
13 years 11 months ago
2007
IEEE
Many DSP algorithms are very computationally intensive. They are typically implemented using an ensemble of processing elements (PEs) operating in parallel. The results from PEs n...
ITNG
2008
IEEE
13 years 11 months ago
2008
IEEE
This paper presents several parallel FFT algorithms with different degree of communication overhead for multiprocessors in Network-on-Chip(NoC) environment. Three different method...
PDPTA
2000
13 years 6 months ago
2000
The paper focuses on coarse-grained dynamically reconfigurable array architectures promising performance and flexibility for different challenging application areas, e. g. future ...