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CSE
2009
IEEE
14 years 1 days ago
On the Design of a Suitable Hardware Platform for Protocol Stack Processing in LTE Terminals
—In this paper we present a design methodology for the identification and development of a suitable hardware platform (including dedicated hardware accelerators) for the data pl...
Sebastian Hessel, David Szczesny, Shadi Traboulsi,...
DATE
2007
IEEE
102views Hardware» more  DATE 2007»
13 years 11 months ago
Efficient testbench code synthesis for a hardware emulator system
: - The rising complexity of modern embedded systems is causing a significant increase in the verification effort required by hardware designers and software developers, leading to...
Ioannis Mavroidis, Ioannis Papaefstathiou
FCCM
2009
IEEE
147views VLSI» more  FCCM 2009»
13 years 9 months ago
FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks
Artificial neural networks are a key tool for researchers attempting to understand and replicate the behaviour and intelligence found in biological neural networks. Software simul...
David Thomas, Wayne Luk
ICCAD
1995
IEEE
110views Hardware» more  ICCAD 1995»
13 years 8 months ago
Fast functional simulation using branching programs
This paper addresses the problem of speeding up functional (delayindependent)logic simulation for synchronousdigital systems. The problem needs very little new motivation – cycl...
Pranav Ashar, Sharad Malik
FPGA
2003
ACM
116views FPGA» more  FPGA 2003»
13 years 10 months ago
Hardware-assisted simulated annealing with application for fast FPGA placement
To truly exploit FPGAs for rapid turn-around development and prototyping, placement times must be reduced to seconds; latebound, reconfigurable computing applications may demand p...
Michael G. Wrighton, André DeHon