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IOLTS
2003
IEEE
97views Hardware» more  IOLTS 2003»
13 years 10 months ago
Error-Injection-Based Failure Characterization of the IEEE 1394 Bus
This paper investigates the behavior of the IEEE 1394 bus in the presence of transient errors in the hardware layers of the protocol. Software-implemented error injection is used ...
D. J. Beauregard, Zbigniew Kalbarczyk, Ravishankar...
ASPDAC
2006
ACM
143views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Constraint-driven bus matrix synthesis for MPSoC
– Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Bus matrix based com...
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...
SAMOS
2005
Springer
13 years 10 months ago
Benchmarking Mesh and Hierarchical Bus Networks in System-on-Chip Context
The performance and area of a System-on-Chip depend on the utilized communication method. This paper presents simulation-based comparison of generic, synthesizable single bus, hie...
Erno Salminen, Tero Kangas, Jouni Riihimäki, ...
VLSID
2006
IEEE
169views VLSI» more  VLSID 2006»
14 years 5 months ago
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks
The two dominant architectural choices for implementing efficient communication fabrics for SoC's have been transaction-based buses and packet-based Networks-onChip (NoC). Bo...
Thomas D. Richardson, Chrysostomos Nicopoulos, Don...