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» Compaction Schemes with Minimum Test Application Time
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ISSS
1997
IEEE
102views Hardware» more  ISSS 1997»
13 years 9 months ago
An Efficient Model for DSP Code Generation: Performance, Code Size, Estimated Energy
This paper presents a model for simultaneous instruction selection, compaction, and register allocation. An arc mapping model along with logical propositions is used to create an ...
Catherine H. Gebotys
DAC
2003
ACM
13 years 11 months ago
Test application time and volume compression through seed overlapping
We propose in this paper an extension on the Scan Chain Concealment technique to further reduce test time and volume requirement. The proposed methodology stems from the architect...
Wenjing Rao, Ismet Bayraktaroglu, Alex Orailoglu
MICS
2010
137views more  MICS 2010»
13 years 4 months ago
Finding Range Minima in the Middle: Approximations and Applications
Abstract. A Range Minimum Query asks for the position of a minimal element between two specified array-indices. We consider a natural extension of this, where our further constrai...
Johannes Fischer, Volker Heun
SCOPES
2004
Springer
13 years 11 months ago
Compact Procedural Implementation in DSP Software Synthesis Through Recursive Graph Decomposition
Abstract. Synthesis of digital signal processing (DSP) software from dataflow-based formal models is an effective approach for tackling the complexity of modern DSP applications. I...
Ming-Yung Ko, Praveen K. Murthy, Shuvra S. Bhattac...
PPOPP
2011
ACM
12 years 8 months ago
Compact data structure and scalable algorithms for the sparse grid technique
The sparse grid discretization technique enables a compressed representation of higher-dimensional functions. In its original form, it relies heavily on recursion and complex data...
Alin Florindor Murarasu, Josef Weidendorfer, Gerri...