138 search results - page 2 / 28 » Compaction-based test generation using state and fault infor... |
DATE
1997
IEEE
13 years 8 months ago
1997
IEEE
A new method for state justi cation is proposed for sequential circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is use...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
We study the effectiveness of functional tests for full scan circuits. Functional tests are important for design validation, and they potentially have a high defect coverage indep...
ICCAD
1998
IEEE
13 years 9 months ago
1998
IEEE
A method is presented for identifying primitive path-delay faults in non-scan sequential circuits and generating robust tests for all robustly testable primitive faults. It uses t...
ET
2010
13 years 2 months ago
2010
This work justifies several quantum gate level fault models and discusses the causal error mechanisms thwarting correct function. A quantum adaptation of the classical test set gen...
ICCAD
1997
IEEE
13 years 9 months ago
1997
IEEE
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...