We propose a new design for an energy-efficient hardware transactional memory (HTM) system for power-aware embedded devices. Prior hardware transactional memory designs proposed a ...
Cesare Ferri, Samantha Wood, Tali Moreshet, R. Iri...
This paper presents CMP Cooperative Caching, a unified framework to manage a CMP’s aggregate on-chip cache resources. Cooperative caching combines the strengths of private and ...
Web caching is a popular technique to improve the performance and scalability of the Web by increasing document availability and enabling download sharing. Distributed cache coope...
Hossam S. Hassanein, Zhengang Liang, Patrick Marti...
The proliferation of Chip Multiprocessors (CMPs) has led to the integration of large on-chip caches. For scalability reasons, a large on-chip cache is often divided into smaller ba...
Ping Zhou, Bo Zhao, Yu Du, Yi Xu, Youtao Zhang, Ju...
- Among all software cache coherence strategaes, the ones that are based on the concept of tamestamps show the greatest potentaal an terms of cache performance. The early tamestamp...