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» Comparing Multiported Cache Schemes
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HIPEAC
2010
Springer
13 years 3 months ago
Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems
We propose a new design for an energy-efficient hardware transactional memory (HTM) system for power-aware embedded devices. Prior hardware transactional memory designs proposed a ...
Cesare Ferri, Samantha Wood, Tali Moreshet, R. Iri...
ISCA
2006
IEEE
182views Hardware» more  ISCA 2006»
13 years 11 months ago
Cooperative Caching for Chip Multiprocessors
This paper presents CMP Cooperative Caching, a unified framework to manage a CMP’s aggregate on-chip cache resources. Cooperative caching combines the strengths of private and ...
Jichuan Chang, Gurindar S. Sohi
ISCC
2002
IEEE
128views Communications» more  ISCC 2002»
13 years 10 months ago
Performance comparison of alternative Web caching techniques
Web caching is a popular technique to improve the performance and scalability of the Web by increasing document availability and enabling download sharing. Distributed cache coope...
Hossam S. Hassanein, Zhengang Liang, Patrick Marti...
ASPDAC
2009
ACM
115views Hardware» more  ASPDAC 2009»
13 years 3 months ago
Frequent value compression in packet-based NoC architectures
The proliferation of Chip Multiprocessors (CMPs) has led to the integration of large on-chip caches. For scalability reasons, a large on-chip cache is often divided into smaller ba...
Ping Zhou, Bo Zhao, Yu Du, Yi Xu, Youtao Zhang, Ju...
ICPP
1996
IEEE
13 years 9 months ago
A Timestamp-based Selective Invalidation Scheme for Multiprocessor Cache Coherence
- Among all software cache coherence strategaes, the ones that are based on the concept of tamestamps show the greatest potentaal an terms of cache performance. The early tamestamp...
Xin Yuan, Rami G. Melhem, Rajiv Gupta