Sciweavers

32 search results - page 2 / 7
» Compiler Optimization for Superscalar Systems: Global Instru...
Sort
View
EMSOFT
2005
Springer
13 years 11 months ago
A sink-n-hoist framework for leakage power reduction
Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies. Recent research efforts have tried to integrate architecture...
Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee
ASPLOS
1989
ACM
13 years 9 months ago
Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor
A very long instruction word (VLIW) processorexploits parallelism by controlling multiple operations in a single instruction word. This paper describes the architecture and compil...
Robert Cohn, Thomas R. Gross, Monica S. Lam, P. S....
ICS
2004
Tsinghua U.
13 years 10 months ago
Evaluating support for global address space languages on the Cray X1
The Cray X1 was recently introduced as the first in a new line of parallel systems to combine high-bandwidth vector processing with an MPP system architecture. Alongside capabili...
Christian Bell, Wei-Yu Chen, Dan Bonachea, Katheri...
CGO
2003
IEEE
13 years 10 months ago
Dynamic Binary Translation for Accumulator-Oriented Architectures
A dynamic binary translation system for a co-designed virtual machine is described and evaluated. The underlying hardware directly executes an accumulator-oriented instruction set...
Ho-Seop Kim, James E. Smith
LCTRTS
2005
Springer
13 years 10 months ago
A dictionary construction technique for code compression systems with echo instructions
Dictionary compression mechanisms identify redundant sequences of instructions that occur in a program. The sequences are extracted and copied to a dictionary. Each sequence is th...
Philip Brisk, Jamie Macbeth, Ani Nahapetian, Majid...