118 search results - page 2 / 24 » Compiler Support for Exploiting Coarse-Grained Pipelined Par... |
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
This paper shows that software pipelining can be an effective technique for code generation for coarse-grained reconfigurable instruction set processors. The paper describes a tec...
IPPS
2005
IEEE
13 years 11 months ago
2005
IEEE
This paper presents a compiler methodology for memoryaware mapping on 2-Dimensional coarse-grained reconfigurable architectures that aims in improving the mapped applications’ p...
IPPS
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper presents a new and retargetable method to identify patterns of instructions with direct support in coarsegrained processing elements (PEs). The method uses a three-addr...
ARC
2007
Springer
13 years 9 months ago
2007
Springer
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
HPCA
1999
IEEE
13 years 9 months ago
1999
IEEE
Symmetric multiprocessors (SMPs) connected with low-latency networks provide attractive building blocks for software distributed shared memory systems. Two distinct approaches hav...