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» Compiler analysis of irregular memory accesses
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IEEEPACT
2009
IEEE
13 years 3 months ago
Adaptive Locks: Combining Transactions and Locks for Efficient Concurrency
Transactional memory is being advanced as an alternative to traditional lock-based synchronization for concurrent programming. Transactional memory simplifies the programming mode...
Takayuki Usui, Reimer Behrends, Jacob Evans, Yanni...
RTSS
2003
IEEE
13 years 11 months ago
Data Caches in Multitasking Hard Real-Time Systems
Data caches are essential in modern processors, bridging the widening gap between main memory and processor speeds. However, they yield very complex performance models, which make...
Xavier Vera, Björn Lisper, Jingling Xue
ISCA
2003
IEEE
110views Hardware» more  ISCA 2003»
13 years 11 months ago
Guided Region Prefetching: A Cooperative Hardware/Software Approach
Despite large caches, main-memory access latencies still cause significant performance losses in many applications. Numerous hardware and software prefetching schemes tolerate th...
Zhenlin Wang, Doug Burger, Steven K. Reinhardt, Ka...
SIGSOFT
2006
ACM
13 years 11 months ago
Bit level types for high level reasoning
Bitwise operations are commonly used in low-level systems code to access multiple data fields that have been packed into a single word. Program analysis tools that reason about s...
Ranjit Jhala, Rupak Majumdar
CODES
2009
IEEE
13 years 9 months ago
TotalProf: a fast and accurate retargetable source code profiler
Profilers play an important role in software/hardware design, optimization, and verification. Various approaches have been proposed to implement profilers. The most widespread app...
Lei Gao, Jia Huang, Jianjiang Ceng, Rainer Leupers...