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» Compiling Smalltalk-80 to a RISC
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MICRO
1994
IEEE
85views Hardware» more  MICRO 1994»
13 years 10 months ago
A high-performance microarchitecture with hardware-programmable functional units
This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Throu...
Rahul Razdan, Michael D. Smith
HICSS
1995
IEEE
128views Biometrics» more  HICSS 1995»
13 years 9 months ago
Instruction Level Parallelism
Abstract. We reexamine the limits of parallelism available in programs, using runtime reconstruction of program data-flow graphs. While limits of parallelism have been examined in...
HPCA
2009
IEEE
14 years 6 months ago
Bridging the computation gap between programmable processors and hardwired accelerators
New media and signal processing applications demand ever higher performance while operating within the tight power constraints of mobile devices. A range of hardware implementatio...
Kevin Fan, Manjunath Kudlur, Ganesh S. Dasika, Sco...
ICCAD
2008
IEEE
108views Hardware» more  ICCAD 2008»
14 years 2 months ago
FBT: filled buffer technique to reduce code size for VLIW processors
— VLIW processors provide higher performance and better efficiency etc. than RISC processors in specific domains like multimedia applications etc. A disadvantage is the bloated...
Talal Bonny, Jörg Henkel
ASPLOS
1987
ACM
13 years 9 months ago
The Effect of Instruction Set Complexity on Program Size and Memory Performance
One potentialdisadvantage of a machine with a reduced instruction. set is that object programs may be substantially larger than those for a machine with a richer, more complex ins...
Jack W. Davidson, Richard A. Vaughan