3 search results - page 1 / 1 » Complexity Bounds for Lookup Table Implementation of Factore... |
IPPS
2000
IEEE
13 years 9 months ago
2000
IEEE
We consider technology mapping from factored form binary leaf-DAG to lookup tables LUTs , such as those found in eld programmable gate arrays. Polynomial time algorithms exist f...
DAC
2010
ACM
13 years 8 months ago
2010
ACM
As device size shrinks to the nanometer range, FPGAs are increasingly prone to manufacturing defects. We anticipate that the ability to tolerate multiple defects will be very impo...
IWANN
2005
Springer
13 years 10 months ago
2005
Springer
In this paper, a fully functional prototype of an asynchronous 4-to-4 Address Event Representation (AER) mapper is presented. AER is an event driven communication protocol original...