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» Compressed Code Execution on DSP Architectures
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ISSS
1999
IEEE
131views Hardware» more  ISSS 1999»
13 years 9 months ago
Compressed Code Execution on DSP Architectures
Decreasing the program size has become an important goal in the design of embedded systems target to mass production. This problem has led to a number of efforts aimed at designin...
Paulo Centoducatte, Ricardo Pannain, Guido Araujo
TCAD
1998
159views more  TCAD 1998»
13 years 4 months ago
Code density optimization for embedded DSP processors using data compression techniques
We address the problem of code size minimization in VLSI systems with embedded DSP processors. Reducing code size reduces the production cost of embedded systems. We use data comp...
Stan Y. Liao, Srinivas Devadas, Kurt Keutzer
ICCD
2000
IEEE
159views Hardware» more  ICCD 2000»
13 years 9 months ago
Evaluating Signal Processing and Multimedia Applications on SIMD, VLIW and Superscalar Architectures
This paper aims to provide a quantitative understanding of the performance of DSP and multimedia applications on very long instruction word (VLIW), single instruction multiple dat...
Deependra Talla, Lizy Kurian John, Viktor S. Lapin...
ICMCS
2006
IEEE
136views Multimedia» more  ICMCS 2006»
13 years 10 months ago
Architecture Analysis for Low-Delay Video Coding
Low-delay video coding is a key technology for video conferencing as well as upcoming remote-monitoring and automotive video applications like rear-view cameras or night vision sy...
Ralf M. Schreier, A. Tushar Iqbal Rahman, Ganesh K...
SCOPES
2004
Springer
13 years 10 months ago
DSP Code Generation with Optimized Data Word-Length Selection
Digital signal processing applications are implemented in embedded systems with fixed-point arithmetic to minimize the cost and the power consumption. To reduce the application ti...
Daniel Menard, Olivier Sentieys