28 search results - page 5 / 6 » Compressed Code Execution on DSP Architectures |
GLVLSI
2009
IEEE
14 years 22 days ago
2009
IEEE
Implementing a custom hardware is not always feasible due to cost and time considerations. No instruction set computer (NISC) architecture is one of the promising direction to des...
CODES
2005
IEEE
13 years 11 months ago
2005
IEEE
As wireless platforms converge to multimedia systems, architectures must converge to support voice, data, and video applications. From a processor architecture perspective, suppor...
CGO
2003
IEEE
13 years 11 months ago
2003
IEEE
Many processor architectures provide a set of addressing modes in their address generation units. For example DSPs (digital signal processors) have powerful addressing modes for e...
ASAP
2005
IEEE
13 years 11 months ago
2005
IEEE
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
ESTIMEDIA
2007
Springer
14 years 4 days ago
2007
Springer
—Modern compression standards such as H.264, DivX, or VC-1 provide astonishing quality at the costs of steadily increasing processing requirements. Therefore, efficient solution...