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CAV
2009
Springer
177views Hardware» more  CAV 2009»
14 years 11 months ago
Software Transactional Memory on Relaxed Memory Models
Abstract. Pseudo-code descriptions of STMs assume sequentially consistent program execution and atomicity of high-level STM operations like read, write, and commit. These assumptio...
Rachid Guerraoui, Thomas A. Henzinger, Vasu Singh
ASIAN
2004
Springer
150views Algorithms» more  ASIAN 2004»
14 years 4 months ago
Concurrent Constraint-Based Memory Machines: A Framework for Java Memory Models
A central problem in extending the von Neumann architecture to petaflop computers with millions of hardware threads and with a shared memory is defining the memory model [Lam79,...
Vijay A. Saraswat
ASPDAC
2004
ACM
106views Hardware» more  ASPDAC 2004»
14 years 4 months ago
A novel memory size model for variable-mapping in system level design
— It is predicted that 70% of the chip area will be occupied by memories in future system-onchips. The minimization of on-chip memory hence becomes increasingly important for cos...
Lukai Cai, Haobo Yu, Daniel Gajski
EIT
2009
IEEE
14 years 5 months ago
System-level memory modeling for bus-based memory architecture exploration
—System-level design (SLD) provides a solution to the challenge of increasing design complexity and time-to-market pressure in modern embedded system designs. In this paper, we p...
Zhongbo Cao, Ramon Mercado, Diane T. Rover
DATE
2005
IEEE
99views Hardware» more  DATE 2005»
14 years 4 months ago
Verification of Embedded Memory Systems using Efficient Memory Modeling
Malay K. Ganai, Aarti Gupta, Pranav Ashar