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» Concurrent Control Systems: From Grafcet to VHDL
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EMSOFT
2006
Springer
13 years 9 months ago
Modeling a system controller for timing analysis
Upper bounds on worst-case execution times, which are commonly called WCET, are a prerequisite for validating the temporal correctness of tasks in a real-time system. Due to the e...
Stephan Thesing
COORDINATION
2006
Springer
13 years 9 months ago
Synthesizing Concurrency Control Components from Process Algebraic Specifications
Process algebraic specifications can provide useful support for the architectural design of software systems due to the possibility of analyzing their properties. In addition to th...
Edoardo Bontà, Marco Bernardo, Jeff Magee, ...
RSP
1999
IEEE
160views Control Systems» more  RSP 1999»
13 years 9 months ago
Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping
SDL is currently gaining interest as a system level specification language for HW/SW codesign. Automated synthesis of SDL in hardware so far had problems with its efficiency. The ...
Oliver Bringmann, Wolfgang Rosenstiel, Annette Mut...
ISSS
2000
IEEE
144views Hardware» more  ISSS 2000»
13 years 9 months ago
Efficient Hardware Controller Synthesis for Synchronous Dataflow Graph in System Level Design
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification in system level design. In the presented design methodology, each node of a data flow gra...
Hyunuk Jung, Kangnyoung Lee, Soonhoi Ha
HT
1993
ACM
13 years 9 months ago
Concurrency Control in Collaborative Hypertext Systems
Traditional concurrency control techniques for database systems (transaction management based on locking protocols) have been successful in many multiuser settings, but these tech...
Uffe Kock Wiil, John J. Leggett