26 search results - page 2 / 6 » Constraint-Based Random Stimuli Generation for Hardware Veri... |
ISQED
2007
IEEE
13 years 11 months ago
2007
IEEE
Design verification has become a bottleneck of modern designs. Recently, simulation-based random verification has attracted a lot of interests due to its effectiveness in uncoveri...
VLSI
2007
Springer
13 years 11 months ago
2007
Springer
— Software simulation remains the most used method for VHDL RTL functional verification. The functional verification process essentially consists of two parts. The first one is t...
DAC
2003
ACM
14 years 6 months ago
2003
ACM
Functional verification is widely acknowledged as the bottleneck in the hardware design cycle. This paper addresses one of the main challenges of simulation based verification (or...
CODES
2005
IEEE
13 years 10 months ago
2005
IEEE
The continuous improvement on the design methodologies and processes has made possible the creation of huge and very complex digital systems. Design verification is one of the mai...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
– An instruction set level reference model was developed for the development of synergistic processing unit (SPU) , which is one of the key components of the cell processor [1][2...