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» Constructing Virtual Architectures on a Tiled Processor
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CGO
2006
IEEE
13 years 11 months ago
Constructing Virtual Architectures on a Tiled Processor
As the amount of available silicon resources on one chip increases, we have seen the advent of ever increasing parallel resources integrated on-chip. Many architectures use these ...
David Wentzlaff, Anant Agarwal
EGH
2004
Springer
13 years 10 months ago
Tile-based texture mapping on graphics hardware
Texture mapping has been a fundamental feature for commodity graphics hardware. However, a key challenge for texture mapping is how to store and manage large textures on graphics ...
Li-Yi Wei
ISCA
2006
IEEE
130views Hardware» more  ISCA 2006»
13 years 4 months ago
Area-Performance Trade-offs in Tiled Dataflow Architectures
: Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and pe...
Steven Swanson, Andrew Putnam, Martha Mercaldi, Ke...
CSSE
2008
IEEE
13 years 11 months ago
Design and Implementation of the Virtual Machine Constructing on Register
: The technology of virtual machines is widely applied in many fields, such as code transplanting, cross-platform computing, and hardware simulation. The main purpose is to simulat...
Weibo Xie, Fu Ting
HPCA
2008
IEEE
14 years 5 months ago
An OS-based alternative to full hardware coherence on tiled CMPs
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...
Christian Fensch, Marcelo Cintra