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FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
14 years 1 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
ISPD
2010
ACM
163views Hardware» more  ISPD 2010»
13 years 11 months ago
A statistical framework for designing on-chip thermal sensing infrastructure in nano-scale systems
Thermal/power issues have become increasingly important with more and more transistors being put on a single chip. Many dynamic thermal/power management techniques have been propo...
Yufu Zhang, Bing Shi, Ankur Srivastava
NOMS
2006
IEEE
189views Communications» more  NOMS 2006»
13 years 10 months ago
Analysis of Firewall Policy Rules Using Data Mining Techniques
— Firewall is the de facto core technology of today's network security and defense. However, the management of firewall rules has been proven to be complex, error-prone, cos...
Korosh Golnabi, Richard K. Min, Latifur Khan, Ehab...
CNSR
2004
IEEE
131views Communications» more  CNSR 2004»
13 years 8 months ago
Fast Flow Classification over Internet
In order to control and manage highly aggregated Internet traffic flows efficiently, we need to be able to categorize flows into distinct classes and to be knowledgeable about the...
A. Oveissian, Kavé Salamatian, Augustin Sou...
GECCO
2008
Springer
107views Optimization» more  GECCO 2008»
13 years 5 months ago
The influence of scaling and assortativity on takeover times in scale-free topologies
In evolving systems, the topological characteristics of population structure have a pronounced impact on the rate of spread of advantageous alleles, and therefore affect selective...
Joshua L. Payne, Margaret J. Eppstein