94 search results - page 1 / 19 » Control Independence in Trace Processors |
MICRO
1999
IEEE
13 years 9 months ago
1999
IEEE
Branch mispredictions are a major obstacle to exploiting instruction-level parallelism, at least in part because all instructions after a mispredicted branch are squashed. However...
EGPGV
2004
Springer
13 years 10 months ago
2004
Springer
This paper investigates assignment strategies (load balancing algorithms) for process farms which solve the problem of online placement of a constant number of independent tasks w...
HPCA
1999
IEEE
13 years 9 months ago
1999
IEEE
Control independence has been put forward as a significant new source of instruction-level parallelism for future generation processors. However, its performance potential under p...
SIGMETRICS
2008
ACM
13 years 4 months ago
2008
ACM
Memory trace analysis is an important technology for architecture research, system software (i.e., OS, compiler) optimization, and application performance improvements. Many appro...
ISPASS
2009
IEEE
13 years 11 months ago
2009
IEEE
Trace-driven simulation of superscalar processors is particularly complicated. The dynamic nature of superscalar processors combined with the static nature of traces can lead to l...