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ISPASS
2009
IEEE

Accurately approximating superscalar processor performance from traces

14 years 4 months ago
Accurately approximating superscalar processor performance from traces
Trace-driven simulation of superscalar processors is particularly complicated. The dynamic nature of superscalar processors combined with the static nature of traces can lead to large inaccuracies in the results, especially when traces contain only a subset of executed instructions for trace reduction. The main problem in the filtered trace simulation is that the trace does not contain enough information with which one can predict the actual penalty of a cache miss. In this paper, we discuss and evaluate three strategies to quantify the impact of a long latency memory access in a superscalar processor when traces have only L1 cache misses. The strategies are based on models about how a cache miss is treated with respect to other cache misses: (1) isolated cache miss model, (2) independent cache miss model, and (3) pairwise dependent cache miss model. Our experimental results demonstrate that the pairwise dependent cache miss model produces reasonably accurate results (4.8% RMS error)...
Kiyeon Lee, Shayne Evans, Sangyeun Cho
Added 19 May 2010
Updated 19 May 2010
Type Conference
Year 2009
Where ISPASS
Authors Kiyeon Lee, Shayne Evans, Sangyeun Cho
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