11 search results - page 2 / 3 » Control Path Oriented Verification of Sequential Generic Cir... |
IFIP
1992
Springer
13 years 9 months ago
1992
Springer
This paper presents a completely systematic design procedure for asynchronous controllers. The initial step is the construction of a signal transition graph (STG, an interpreted P...
AHS
2007
IEEE
13 years 9 months ago
2007
IEEE
This paper presents a mechanism for the separation of control and data flow in NoC-based SoCs consisting of multiple heterogeneous reconfigurable IP cores. This mechanism enables ...
DAC
1994
ACM
13 years 9 months ago
1994
ACM
A low overhead DFT technique, called clock-grouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault co...
FMCAD
2008
Springer
13 years 7 months ago
2008
Springer
el Sequential Memory Abstraction for Model Checking Per Bjesse Advanced Technology Group Synopsys Inc. Many designs intermingle large memories with wide data paths and nontrivial c...
MICRO
2000
IEEE
13 years 9 months ago
2000
IEEE
Register integration (or simply integration) is a mechanism for incorporating speculative results directly into a sequential execution using data-dependence relationships. In this...