360 search results - page 3 / 72 » Control network generator for latency insensitive designs |
HOTI
2005
IEEE
13 years 11 months ago
2005
IEEE
— A crucial part of any high-performance computing system is its interconnection network. In the OSMOSIS project, Corning and IBM are jointly developing a demonstrator interconne...
ICETET
2009
IEEE
14 years 12 days ago
2009
IEEE
Abstract— Design of Network on chip architectures for multimedia applications is being widely studied. This involves design decisions at various levels of hierarchy. Topology des...
CODES
2007
IEEE
14 years 2 days ago
2007
IEEE
Memory requirements of intellectual property components (IP) in contemporary multi-processor systems-on-chip are increasing. Large high-speed external memories, such as DDR2 SDRAM...
NSDI
2004
13 years 7 months ago
2004
Designing a wide-area distributed hash table (DHT) that provides high-throughput and low-latency network storage is a challenge. Existing systems have explored a range of solution...
GI
2001
Springer
13 years 10 months ago
2001
Springer
Abstract—Advanced network and media applications such as multimedia streaming and Internet telephony are becoming an integral part of the Internet. Reservation protocols, such as...