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VLSID
2005
IEEE
116views VLSI» more  VLSID 2005»
14 years 5 months ago
A Quasi-Delay-Insensitive Method to Overcome Transistor Variation
Synchronous design methods have intrinsic performance overheads due to their use of the global clock and timing assumptions. In future manufacturing processes not only may it beco...
C. Brej, Jim D. Garside
CDES
2010
184views Hardware» more  CDES 2010»
13 years 3 months ago
Delay-Insensitive Cell Matrix
This paper describes the design of a delay-insensitive (DI) Cell Matrix. This architecture allows for massively parallel, self-determined operation and can be used to implement reg...
Scott Smith, David Roclin, Jia Di
CHES
2006
Springer
146views Cryptology» more  CHES 2006»
13 years 9 months ago
Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits
This paper presents a Path Swapping (PS) method which enables to enhance the security of Quasi Delay Insensitive Asynchronous Circuits against Power Analysis (PA) attack. This appr...
G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin
AC
2002
Springer
13 years 5 months ago
A Programming Approach to the Design of Asynchronous Logic Blocks
Abstract. Delay-Insensitive Sequential Processes is a structured, parallel programming language. It facilitates the clear, succinct and precise specification of the way an asynchro...
Mark B. Josephs, Dennis P. Furey
EENERGY
2010
13 years 9 months ago
Optimal sleep patterns for serving delay-tolerant jobs
Sleeping is an important method to reduce energy consumption in many information and communication systems. In this paper we focus on a typical server under dynamic load, where en...
Ioannis Kamitsos, Lachlan L. H. Andrew, Hongseok K...