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» Core-Selectability in Chip Multiprocessors
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MICRO
2010
IEEE
140views Hardware» more  MICRO 2010»
13 years 2 months ago
STEM: Spatiotemporal Management of Capacity for Intra-core Last Level Caches
Efficient management of last level caches (LLCs) plays an important role in bridging the performance gap between processor cores and main memory. This paper is motivated by two key...
Dongyuan Zhan, Hong Jiang, Sharad C. Seth
MICRO
2010
IEEE
128views Hardware» more  MICRO 2010»
13 years 2 months ago
Adaptive and Speculative Slack Simulations of CMPs on CMPs
Current trends signal an imminent crisis in the simulation of future CMPs (Chip MultiProcessors). Future micro-architectures will offer more and more thread contexts to execute pa...
Jianwei Chen, Lakshmi Kumar Dabbiru, Daniel Wong, ...
WWW
2005
ACM
14 years 5 months ago
A multi-threaded PIPELINED Web server architecture for SMP/SoC machines
Design of high performance Web servers has become a recent research thrust to meet the increasing demand of networkbased services. In this paper, we propose a new Web server archi...
Gyu Sang Choi, Jin-Ha Kim, Deniz Ersoz, Chita R. D...