27 search results - page 3 / 6 » Core-aware memory access scheduling schemes |
CONCURRENCY
2006
13 years 5 months ago
2006
To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
IOLTS
2002
IEEE
13 years 10 months ago
2002
IEEE
This paper proposes a new solution for the diagnosis of faults into embedded RAMs, currently under evaluation within STMicroelectronics. The proposed scheme uses dedicated circuit...
INFOCOM
2003
IEEE
13 years 11 months ago
2003
IEEE
— Multiuser diversity refers to a type of diversity present across different users in a fading environment. This diversity can be exploited by scheduling transmissions so that us...
HPCA
2005
IEEE
14 years 6 months ago
2005
IEEE
Memory system optimizations have been well studied on single-threaded systems; however, the wide use of simultaneous multithreading (SMT) techniques raises questions over their ef...
DAC
2002
ACM
14 years 6 months ago
2002
ACM
Previous work on DRAM power-mode management focused on hardware-based techniques and compiler-directed schemes to explicitly transition unused memory modules to low-power operatin...