A Performance Comparison of DRAM Memory System Optimizations for SMT Processors

Memory system optimizations have been well studied on single-threaded systems; however, the wide use of simultaneous multithreading (SMT) techniques raises questions over their effectiveness in the new context. In this study, we thoroughly evaluate contemporary multi-channel DDR SDRAM and Rambus DRAM systems in SMT systems, and search for new thread-aware DRAM optimization techniques. Our major findings are: (1) in general, increasing the number of threads tends to increase the memory concurrency and thus the pressure on DRAM systems, but some exceptions do exist; (2) the application performance is sensitive to memory channel organizations, e.g. independent channels may outperform ganged organizations by up to 90%; (3) the DRAM latency reduction through improving row buffer hit rates becomes less effective due to the increased bank contentions; and (4) thread-aware DRAM access scheduling schemes may improve performance by up to 30% on workload mixes of memory-intensive applications. I...

• Type: Conference
• Year: 2005
• Where: HPCA
• Authors: Zhichun Zhu, Zhao Zhang
• Keywords: Computer Architecture, DRAM Latency Reduction, DRAM Optimization Techniques, HPCA 2005, Rambus DRAM Systems