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» Correct-by-construction microarchitectural pipelining
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ASPDAC
2007
ACM
100views Hardware» more  ASPDAC 2007»
13 years 8 months ago
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning
- For modern processor designs in nanometer technologies, both block and interconnect pipelining are needed to achieve multi-gigahertz clock frequency, but previous approaches cons...
Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong,...
ASPDAC
2005
ACM
100views Hardware» more  ASPDAC 2005»
13 years 6 months ago
Microarchitecture evaluation with floorplanning and interconnect pipelining
— As microprocessor technology continues to scale into the nanometer regime, recent studies show that interconnect delay will be a limiting factor for performance, and multiple c...
Ashok Jagannathan, Hannah Honghua Yang, Kris Konig...
MSCS
2008
86views more  MSCS 2008»
13 years 4 months ago
Maurer computers for pipelined instruction processing
We model micro-architectures with non-pipelined instruction processing and pipelined instruction processing, using Maurer machines, basic thread algebra and program algebra. We sho...
Jan A. Bergstra, C. A. Middelburg
DATE
2010
IEEE
142views Hardware» more  DATE 2010»
13 years 6 months ago
Automatic microarchitectural pipelining
Abstract--This paper presents a method for automatic microarchitectural pipelining of systems with loops. The original specification is pipelined by performing provably-correct tra...
Marc Galceran Oms, Jordi Cortadella, Dmitry Bufist...
IPPS
2007
IEEE
13 years 11 months ago
Modeling Modern Micro-architectures using CASL
We overview CASL, the CoGenT Architecture Specification Language, a mixed behavioral-structure architecture description language designed to facilitate fast prototyping and tool ...
Edward K. Walters II, J. Eliot B. Moss, Trek S. Pa...