- For modern processor designs in nanometer technologies, both block and interconnect pipelining are needed to achieve multi-gigahertz clock frequency, but previous approaches cons...
Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong,...
— As microprocessor technology continues to scale into the nanometer regime, recent studies show that interconnect delay will be a limiting factor for performance, and multiple c...
We model micro-architectures with non-pipelined instruction processing and pipelined instruction processing, using Maurer machines, basic thread algebra and program algebra. We sho...
Abstract--This paper presents a method for automatic microarchitectural pipelining of systems with loops. The original specification is pipelined by performing provably-correct tra...
Marc Galceran Oms, Jordi Cortadella, Dmitry Bufist...
We overview CASL, the CoGenT Architecture Specification Language, a mixed behavioral-structure architecture description language designed to facilitate fast prototyping and tool ...
Edward K. Walters II, J. Eliot B. Moss, Trek S. Pa...