68 search results - page 2 / 14 » Coverage in interpolation-based model checking |
CAV
2001
Springer
13 years 10 months ago
2001
Springer
In formal verification, we verify that a system is correct with respect to a specification. When verification succeeds and the system is proven to be correct, there is still a q...
ISVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
Formal verification has become an important step in circuit and system design. A prominent technique is Bounded Model Checking (BMC) which is widely used in industry. In BMC it i...
DAC
2010
ACM
13 years 9 months ago
2010
ACM
Coverage is a means to quantify the quality of a system specification, and is frequently applied to assess progress in system validation. Coverage is a standard measure in testin...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
Practitioners of formal property verification often work around the capacity limitations of formal verification tools by breaking down properties into smaller properties that ca...
FATES
2004
Springer
13 years 10 months ago
2004
Springer
This paper presents a method for reducing the cost of test generation. A spanning set for a coverage criterion is a set of entities such that exercising every entity in the spannin...