19 search results - page 4 / 4 » Covert and Side Channels Due to Processor Architecture |
ASAP
2009
IEEE
14 years 2 months ago
2009
IEEE
The advent of the mobile age has heavily changed the requirements of today’s communication devices. Data transmission over interference-prone wireless channels requires addition...
HPCA
2005
IEEE
14 years 5 months ago
2005
IEEE
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
DFT
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper discusses a hybrid optoelectronic scheme for a new interconnection network, "Tori connected mESHes (TESH)". The major features of TESH are the following: it i...
DSN
2007
IEEE
13 years 11 months ago
2007
IEEE
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...