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CHES
2007
Springer
126views Cryptology» more  CHES 2007»
13 years 11 months ago
How to Maximize the Potential of FPGA Resources for Modular Exponentiation
This paper describes a modular exponentiation processing method and circuit architecture that can exhibit the maximum performance of FPGA resources. The modular exponentiation arch...
Daisuke Suzuki
FCCM
1998
IEEE
99views VLSI» more  FCCM 1998»
13 years 9 months ago
FPGA-Based Architecture Evaluation of Cryptographic Coprocessors for Smartcards
In 1996, about 600 million IC-cards were manufactured worldwide. Due to very small die sizes (max. 25 mm2 ) smartcards encounter more severe restrictions than conventional coproces...
Hagen Ploog, Dirk Timmermann
FCCM
2006
IEEE
195views VLSI» more  FCCM 2006»
13 years 11 months ago
A Parallel Hardware Architecture for fast Gaussian Elimination over GF(2)
This paper presents a hardware-optimized variant of the well-known Gaussian elimination over GF(2) and its highly efficient implementation. The proposed hardware architecture, we...
Andrey Bogdanov, M. C. Mertens
DATAMINE
1999
113views more  DATAMINE 1999»
13 years 5 months ago
A Fast Parallel Clustering Algorithm for Large Spatial Databases
The clustering algorithm DBSCAN relies on a density-based notion of clusters and is designed to discover clusters of arbitrary shape as well as to distinguish noise. In this paper,...
Xiaowei Xu, Jochen Jäger, Hans-Peter Kriegel
SIGMOD
2010
ACM
166views Database» more  SIGMOD 2010»
13 years 10 days ago
FAST: fast architecture sensitive tree search on modern CPUs and GPUs
In-memory tree structured index search is a fundamental database operation. Modern processors provide tremendous computing power by integrating multiple cores, each with wide vect...
Changkyu Kim, Jatin Chhugani, Nadathur Satish, Eri...